Integrating metal layers with ultra low-K dielectrics

ABSTRACT

In forming a layer of a semiconductor wafer, a dielectric layer is deposited on the semiconductor wafer. The dielectric layer includes material having a low dielectric constant. Recessed and non-recessed areas are formed in the dielectric layer. A metal layer is deposited on the dielectric layer to fill the recessed areas and cover the non-recessed areas. The metal layer is then electropolished to remove the metal layer covering the non-recessed areas while maintaining the metal layer in the recessed areas.

CROSS-REFERENCE TO RELATED APPLICATIONS

The present application claims priority of an earlier filed provisionalapplication U.S. Ser. No. 60/233,587, entitled METHOD FOR INTEGRATINGCOPPER WITH ULTRA-LOW K DIELECTRICS, filed on Sep. 18, 2000, the entirecontent of which is incorporated herein by reference.

BACKGROUND

1. Field of the Invention

The present invention generally relates to interconnections withinlayers of a semiconductor wafer. More particularly, the presentinvention relates to interconnections in low-K dielectric materials andultra low-K dielectric materials.

2. Description of the Related Art

In general, semiconductor devices are manufactured or fabricated ondisks of semiconducting materials called wafers or slices. Moreparticularly, wafers are initially sliced from a silicon ingot. Thewafers then undergo multiple masking, etching, and deposition processesto form the electronic circuitry of semiconductor devices.

During the past decades, the semiconductor industry has increased thepower of semiconductor devices in accordance with Moore's law, whichpredicts that the power of semiconductor devices will double every 18months. This increase in the power of semiconductor devices has beenachieved in part by decreasing the feature size (i.e., the smallestdimension present on a device) of these semiconductor devices. In fact,the feature size of semiconductor devices has quickly gone from 0.35microns to 0.25 microns, and now to 0.18 microns. Undoubtedly, thistrend toward smaller semiconductor devices is likely to proceed wellbeyond the sub-0.18 micron stage.

However, one potential limiting factor to developing more powerfulsemiconductor devices is the increasing signal delays at theinterconnections (the lines of conductors, which connect elements of asingle semiconductor device and/or connect any number of semiconductordevices together). As the feature size of semiconductor devices hasdecreased, the density of interconnections on the devices has increased.The closer proximity of interconnections, however, increases theline-to-line capacitance of the interconnections, which results ingreater signal delay at the interconnections. In general,interconnection delays have been found to increase with the square ofthe reduction in feature size. In contrast, gate delays have been foundto decrease linearly with the reduction in feature size. As such, thereis generally a net increase in overall delays with a reduction infeature size.

One conventional approach to compensate for this increase ininterconnection delay has been to add more layers of metal. However,this approach has the disadvantage of increasing production costsassociated with forming the additional layers of metal. Furthermore,these additional layers of metal generate additional heat, which can beadverse to both chip performance and reliability.

An alternative approach to compensate for the increase ininterconnection delay is to use dielectric materials having lowdielectric constants (low-K dielectrics). However, because low-Kdielectric materials have porous microstructures, they also have lowermechanical integrity and thermal conductivity than other dielectricmaterials. Consequently, low-K dielectric materials typically cannotsustain the stress and pressure applied to them during a conventionaldamascene process.

In a conventional damascene process, metal is patterned withincanal-like trenches and/or via. The deposited metal is then typicallypolished back using chemical mechanical polishing (CMP). In general,depending on the interconnection structure design, anywhere from half amicron to 1.5 millimeters of metal can be polished.

However, when metal is patterned within trenches and/or via of a low-Kdielectric material, and then polished back using CMP, the low-Kdielectric material can fracture or pull away from the metal within thetrenches and/or via due to the stress and pressure of CMP. Consequently,strong or rigid structures have been formed within the low-K dielectricmaterials to help them sustain the stress and pressure applied duringCMP. However, building such structures within the low-K dielectricmaterials can be costly and can increase the interconnection delayswithin the device that the low-K dielectric materials were intended toreduce.

SUMMARY

The present invention relates to forming a layer of a semiconductorwafer. In accordance with one aspect of the present invention, adielectric layer is deposited on the semiconductor wafer. The dielectriclayer includes material having a low dielectric constant. Recessed andnon-recessed areas are formed in the dielectric layer. A metal layer isdeposited on the dielectric layer to fill the recessed areas and coverthe non-recessed areas. The metal layer is then electropolished toremove the metal layer covering the non-recessed areas while maintainingthe metal layer in the recessed areas.

DESCRIPTION OF THE DRAWING FIGURES

The present invention can be best understood by reference to thefollowing detailed description taken in conjunction with theaccompanying drawing figures, in which like parts may be referred to bylike numerals:

FIG. 1 is a cross-sectional view of an exemplary semiconductor wafer;

FIGS. 2A–2H illustrate, in cross-sectional view, an exemplary embodimentof the various steps of a damascene process;

FIG. 3 illustrates, in cross-sectional view, an exemplaryelectropolishing nozzle;

FIG. 4 is a flow chart illustrating the steps of a damascene process, inaccordance with various embodiments of the present invention;

FIGS. 5A–5H illustrate, in cross-sectional view, an alternativeembodiment of the various steps of a damascene process;

FIGS. 6A–6J illustrate, in cross-sectional view, an exemplary embodimentof the various steps of a damascene process;

FIG. 7 illustrates, in cross-sectional view, an exemplaryelectropolishing nozzle;

FIGS. 8A–8J illustrate, in cross-sectional view, another exemplaryembodiment of the various steps of a damascene process;

FIGS. 9A–9H illustrate, in cross-sectional view, another exemplaryembodiment of the various steps of a damascene process;

FIGS. 10A–10J illustrate, in cross-sectional view, an alternativeembodiment of the various steps of a damascene process;

FIGS. 11A–11J illustrate, in cross-sectional view, another alternativeembodiment of the various steps of a damascene process;

FIGS. 12A–12H illustrate, in cross-sectional view, another alternativeembodiment of the various steps of a damascene process.

DETAILED DESCRIPTION

In order to provide a more thorough understanding of the presentinvention, the following description sets forth numerous specificdetails, such as specific configurations, parameters, examples, and thelike. It should be recognized, however, that such description is notintended as a limitation on the scope of the present invention, but isintended to provide a better description of the exemplary embodiments.

With reference to FIG. 1, an exemplary semiconductor wafer 100 isdepicted having layers 104, 106, 108, 110, and 112 formed on a substrate102. Substrate 102 preferably includes silicon, but can include varioussemiconductor materials, such as gallium arsenide and the like,depending on the particular application. Furthermore, layer 104 caninclude gates 114, lines 116, and plugs 115. Similarly, layers 106, 108,and 110 can include lines 118, 120, 122, and plugs 117, 119, 121,respectively.

Generally, plugs can connect lines in different layers, and can connectlines to substrate 102, as shown in layer 104. More particularly, plugscan connect lines to sources and drains in substrate 102 that areassociated with gates 114. Additionally, although some of the lines inlayers 106, 108, and 110 do not connect to plugs in this cross-section,these lines can have plugs connecting to them in other cross-sections.Furthermore, as shown, lines can be wider than the plugs connected tothem. However, it should be recognized that, in some applications, linesmay not necessarily be wider than the plugs connected to them.

Furthermore, it should be recognized that although semiconductor wafer100 is shown in FIG. 1 with five layers 104, 106, 108, 110, and 112formed on substrate 102, semiconductor wafer 100 can include any numberof layers formed on substrate 102. Moreover, it should be recognizedthat semiconductor wafer 100 can include any number of gates, lines, andplugs within these layers.

In FIGS. 2A–2H, cross-sectional views of a layer 202 are shown toillustrate various steps of an exemplary damascene process used to formlines, such as lines 120 in section 124 of FIG. 1. More particularly, aswill be described in greater detail below, in a damascene process,canal-like trenches and via are formed in a dielectric layer. Thetrenches and via are filled with a conducting material to form lines andplugs, respectively. It should be noted, however, that the process shownin this exemplary embodiment can be used to form gates or any otherstructure of semiconductor device.

With reference now to FIG. 2A, a dielectric layer 204 can be formed on apreviously formed layer of a semiconductor wafer by any convenientmethod, such as chemical vapor deposition (CVD), physical vapordeposition (PVD), atomic layer deposition (ALD), a spin-on coatingprocess followed by curing and drying steps, and the like. In thepresent embodiment, dielectric layer 204 can include various materialshaving dielectric constant (K) values less than that of silicon dioxide,which is about 4.0. Examples of materials having K values less than thatof silicon dioxide are listed in Tables 1 and 2 below:

TABLE 1 Approximate Preferred Deposition Dielectric Material K ValueMethod(s) Fluorinated silicate glass 3.2–3.6 CVD Polyimides 3.0–3.5Spin-on coating Fluorinated polyimides 2.5–3.3 Spin-on coatingHybrids/composites 2.8–3.0 Spin-on coating Siloxanes 2.7–2.9 Spin-oncoating Organic polymers 2.3–2.7 Spin-on coating α-C:F 2.1–2.5 CVDSi—O—C 2.4–2.8 CVD Parylenes/fluorinated 2.2–2.6 CVD parylenes

TABLE 2 Approximate Preferred Deposition Dielectric Material K ValueMethod(s) Organic polymers 2.3–2.7 Spin-on coating α-C:F 2.1–2.5 CVDSi—O—C 2.4–2.8 CVD Parylenes/fluorinated 2.2–2.6 CVD parylenes PTFE  2.0 Spin-on coating (Polyterafluoroethylene) Nanoporous silica <2.0Spin-on coating Nanoporous organic <2.0 Spin-on coatingIt should be recognized, however, that dielectric layer 204 can includeany materials having K values less than that of silicon dioxide.Generally, low-K materials provide better electrical isolation thansilicon dioxide, thereby allowing the formation of semiconductor deviceswith smaller feature sizes than those that can be formed using silicondioxide.

In the present exemplary process, after dielectric layer 204 is formedon a previously formed layer, insulation layer 206 can be deposited ontop of dielectric layer 204 by any convenient deposition process, suchas CVD, PVD, ALD, a spin-on coating process followed by curing anddrying steps, and the like. As will be described below, insulation layer206 can include materials having anti-reflective properties andresistance to lithography and etching methods, such as silicon nitride.

It should be recognized that any reference to depositing a firstmaterial “on top of” or “on” a second material in this or any otherembodiment can include depositing the first material on one or moreintermediate material that may be formed on the second material, unlessotherwise explicitly stated. Furthermore, it should be recognized thatany reference to depositing a first material “on top of” or “on” asecond material in this or any other embodiment should not be viewed asbeing limited to a particular orientation. For example, the firstmaterial can be deposited below the first material if the materials arebeing formed on the bottom side of a wafer.

After insulation layer 206 is deposited on top of dielectric layer 204,a dielectric layer 208 can be deposited on top of insulation layer 206by any convenient method, such as CVD, PVD, ALD, a spin-on coatingprocess followed by curing and drying steps, and the like. Dielectriclayer 208 can include various materials having dielectric constant (K)values less than that of silicon dioxide, such as those listed in Tables1 and 2. It should be recognized, however, that dielectric layer 204 caninclude any materials having K values less than about 4.0.

Referring now to FIG. 2B, recessed areas 210 and non-recessed areas 211can then be formed in dielectric layer 208 by any convenient method,such as by lithography and etching, and the like. More particularly, thelithography method used can include UV lithography, deep UV lithography,x-ray lithography, electron lithography, ion beam lithography, and thelike. As shown, insulation layer 206 can separate dielectric layer 204from dielectric layer 208, and can therefore reduce the amount ofdielectric layer 204 etched away or otherwise damaged during alithography and etching process used to form the recessed areas 210 indielectric layer 208. Moreover, insulation layer 206 can includeanti-reflective properties that can reduce the reflection of light or UVrays from insulation layer 206 and any layers below that could interferewith a lithography and etching process used to form the recessed areas210 in dielectric layer 208.

Next, with reference to FIG. 2C, a barrier layer 212 can be deposited ontop of dielectric layer 208 by any convenient deposition method, such asCVD, PVD, ALD, a spin-on coating process followed by curing and dryingsteps, and the like. As depicted, barrier layer 212 can also line thewalls of recessed areas 210. Additionally, barrier layer 212 can includea material that can prevent the diffusion or leaching of a subsequentlyformed a metal layer 216 (FIG. 2D), as will be described below, intodielectric layer 208, which can have a porous microstructure.Furthermore, barrier layer 212 can be formed from a conductive material,which adheres to both dielectric layer 208 and metal layer 216 (FIG.2D).

As will also be described below, metal layer 216 (FIG. 2D) is preferablyformed from copper. Accordingly, in the present embodiment, barrierlayer 212 can include material resistant to diffusion of copper, such astitanium, tantalum, tungsten, titanium-nitride, tantalum-nitride,tungsten-nitride, tantalum silicon nitride, tungsten silicon nitride,and the like. It should be recognized, however, that barrier layer 212can be omitted in some applications. For example, when dielectric layer208 is formed from a material that is resistant to the diffusion ofcopper, or when the diffusion of copper into dielectric layer 208 willnot adversely affect the performance of the semiconductor device,barrier layer 212 can be omitted.

After barrier layer 212 is deposited on top of dielectric layer 208, aseed layer 214 can be deposited on top of barrier layer 212 by anyconvenient method, such as CVD, PVD, ALD, a spin-on coating processfollowed by curing and drying steps, and the like. Seed layer 214 caninclude the same material as subsequently formed metal layer 216 (FIG.2D), as will be described below, in order to facilitate the depositionand bonding of metal layer 216 (FIG. 2D) onto barrier layer 212 ordielectric layer 208 if no barrier layer 212 is used. Accordingly, inthe present embodiment, seed layer 214 preferably includes copper. Itshould be recognized, however, that seed layer 214 can be omitted insome applications. For example, when metal layer 216 (FIG. 2D) isdeposited by methods such as PVD, CVD, ALD, or a spin-on coating processfollowed by curing and drying steps, seed layer 214 may not benecessary.

Next, with reference to FIG. 2D, metal layer 216 can be deposited ontoseed layer 214 (FIG. 2C) by any convenient method, such aselectroplating, electroless plating, PVD, CVD, ALD, a spin-on coatingprocess followed by curing and drying steps, and the like. As depicted,metal layer 216 can fill recessed areas 210 (FIG. 2C) and covernon-recessed areas 211 (FIG. 2C). Additionally, metal layer 216 caninclude various electrically conductive materials, such as copper,aluminum, nickel, chromium, zinc, cadmium, silver, gold, rhodium,palladium, platinum, tin, lead, iron, indium, and the like. Furthermore,it should be recognized that metal layer 628 can include an alloy of anyof the various electrically conductive materials.

In the present exemplary embodiment, metal layer 216 preferably includescopper, and can be electroplated onto seed layer 214 (FIG. 2C) using theelectroplating apparatus and method described in U.S. patentapplication, Ser. No. 09/232,864, entitled PLATING APPARATUS AND METHOD,filed on Jan. 15, 1999, the entire content of which is incorporatedherein by reference. As noted above, the deposition and bonding of metallayer 216 onto barrier layer 212, or dielectric layer 208 if no barrierlayer 212 is used, during the electroplating process can be facilitatedby a previously formed seed layer 214 (FIG. 2C). Additionally, as alsonoted above, a previously formed barrier layer 212 can prevent metallayer 216 and an associated seed layer 214 (FIG. 2C), if used, fromdiffusing or leaching into dielectric layer 208. However, it should berecognized that metal layer 216 can be deposited directly ontodielectric layer 208 or barrier layer 212 in some applications.

Now with reference to FIG. 2E, after metal layer 216 is deposited ontodielectric layer 208, metal layer 216 can then be removed fromnon-recessed areas 211 of dielectric layer 208 by any convenient method,such as electropolishing, chemical-mechanical polishing (CMP), and thelike. As shown, removing metal layer 216 from non-recessed areas 211 ofdielectric layer 208 can include removing metal layer 216 fromnon-recessed areas 211 of any intermediate layer, such as barrier layer212 and the like, that are deposited on dielectric layer 208.Furthermore, as shown, in the present embodiment, metal layer 216 isremoved from non-recessed areas 211 of dielectric layer 208 whilemaintaining the metal layer 216 within recessed areas 210 of dielectriclayer 208.

In the present exemplary embodiment, metal layer 216 is preferablyelectropolished from dielectric layer 208. For example, with referenceto FIG. 3, metal layer 216 on semiconductor wafer 100 can beelectropolished with nozzle 300. More particularly, nozzle 300 can applyan electrolyte stream 304 to metal layer 216. This electrolyte stream304 can be charged by an electrode 302. Furthermore, as depicted, apower supply 306, which can operate at a constant current or constantvoltage mode, can apply opposing charges to electrode 302 and metallayer 216. Accordingly, when electrolyte stream 304 is chargedpositively relative to metal layer 216, metal ions can be removed fromthe portion of metal layer 216 in contact with the electrolyte stream304.

In the present example, electrolyte stream 304 can be applied to metallayer 216 along a spiral path by rotating semiconductor wafer 100 aboutaxis Y and translating semiconductor wafer 100 along axis X. By applyingelectrolyte stream 304 in a spiral path, metal layer 216 can beuniformly electropolished. Alternatively, electrolyte stream 304 can beapplied to metal layer 216 by holding semiconductor wafer 100 stationaryand moving nozzle 300 to apply electrolyte stream 304 to discreteportions of metal layer 216. Yet another alternative can include movingboth semiconductor wafer 100 and nozzle 300 to apply electrolyte stream304 to discrete portions of metal layer 216. For a more detaileddescription of electropolishing, see U.S. patent application Ser. No.09/497,894, entitled METHODS AND APPARATUS FOR ELECTROPOLISHING METALINTERCONNECTIONS ON SEMICONDUCTOR DEVICES, filed on Feb. 4, 2000, whichis incorporated in its entirety herein by reference.

With reference again to FIG. 2E, because electropolishing can exert lowlateral stress on dielectric layer 208, metal layer 216 can beelectropolished from dielectric layer 208 without fracturing dielectriclayer 208, separating metal layer 216 from dielectric layer 208, orotherwise damaging dielectric layer 208, metal layer 216, or barrierlayer 212.

Accordingly, electropolishing can provide advantages over conventionalremoval processes. In particular, polishing metal layer 216 fromdielectric layer 208 with CMP can cause dielectric layer 208 to fractureor pull away from metal layer 216 due to the stress and pressure of CMP.Additionally, because electropolishing can be essentially stressless,constructing additional structures within dielectric layer 208 toincrease the mechanical integrity of dielectric layer 208 may beunnecessary. However, it should be recognized that the present inventioncan be used with a dielectric layer 208 constructed with additionalstructures. Furthermore, it should also be recognized that a portion ofmetal layer 216 can be removed by CMP, or by any other process, beforemetal layer 216 is removed from non-recessed areas 211 of dielectriclayer 208 by electropolishing.

Referring now to FIG. 2F, after metal layer 216 is removed fromnon-recessed areas 211 (FIG. 2E) of dielectric layer 208, barrier layer212 can be removed from non-recessed areas 211 (FIG. 2E) of dielectriclayer 208 by any convenient method, such as wet etching, dry chemicaletching, dry plasma etching, and the like. As noted above, however, insome applications, barrier layer 212 may not be used.

After barrier layer 212 is removed, with reference to FIG. 2G, aninsulation layer 218 can be deposited on top of dielectric layer 208 byany convenient deposition process, such as CVD, PVD, ALD, a spin-oncoating process followed by curing and drying steps, and the like. Asshown, insulation layer 218 can also contact barrier layer 212 and metallayer 216. Furthermore, insulation layer 218 can separate layer 202 fromany layers that may be deposited on top of layer 202. Additionally,insulation layer 218 can include anti-reflective properties that canreduce the reflection of light or UV rays from insulation layer 218 andany layers below that could interfere with a lithography and etchingprocess performed on any layers deposited above layer 202. Moreover,insulation layer 206 can reduce the amount of materials in layer 202etched away or otherwise damaged during lithography and etchingprocesses that may be performed on layers deposited above layer 202.Accordingly, in the present exemplary embodiment, insulation layer 218can include materials that are anti-reflective and resistant tolithography and etching methods, such as silicon nitride.

The above process for forming layer 202 in the present embodiment can berepeated to form additional layers on top of layer 202. For instance,with reference to FIG. 2H, dielectric layer 220 can be formed on top oflayer 202, as part of another layer 222. Trenches and via can then beformed in dielectric layer 220 to form lines and plugs, respectively,that can contact metal layer 216 in layer 202.

In addition, although the present embodiment is described in conjunctionwith forming lines in a layer of a semiconductor wafer, it should berecognized that the above explained process can also be used to formgates, via, or any other semiconductor device structure. For instance,dielectric layer 204, as depicted in FIGS. 2A–2H can be substituted withsubstrate 102 (FIG. 1), and recessed areas 210 can be used to formgates.

With reference to FIG. 4, a flow chart illustrating an exemplarydamascene process is shown. In step 400, a dielectric layer is formed ona previously formed layer or on the substrate of a semiconductor wafer.In step 402, a metal layer is deposited on the dielectric layer. In step404, the deposited metal layer is electropolished from the dielectriclayer.

It should be recognized, however, that various modifications can be madeto the process depicted in the flow chart. For example, the step ofremoving a portion of the metal layer using CMP can be added betweensteps 402 and 404. Additionally, it should be recognized that each ofthe steps depicted in FIG. 4 can include numerous steps. For example,step 400 can include providing a low-K dielectric material havingrecessed areas formed thereon. Moreover, it should be recognized thatthe steps depicted in FIG. 4 can be used for any damascene process,including a single-damascene process or a dual-damascene process.

In FIGS. 5A–5H, an alternative embodiment of the present invention isshown. The embodiment of FIGS. 5A–5H is similar in many respects to thatof FIGS. 2A–2H, except that, with reference to FIG. 5A, a protectivelayer 500 can be deposited on top of dielectric layer 208 by anyconvenient method, such as PVD, CVD, ALD, a spin-on coating processfollowed by curing and drying steps, and the like. Similarly, withreference to FIG. 5H, a protective layer 502 can be deposited on top ofdielectric layer 220.

With reference now to FIGS. 5E and 5F, protective layer 500 can separatebarrier layer 212 from dielectric layer 208, and can therefore protectdielectric layer 208 from damage, such as abrasion or corrosion, whenbarrier layer 212 is removed by any convenient method, such as wetetching, dry chemical etching, dry plasma etching, and the like.Additionally, with reference to FIGS. 5F–5H, protective layer 500 canremain on non-recessed areas 211 of dielectric layer 208 during variousstages following the removal of barrier layer 212. Accordingly,protective layer 500 can include a material that is resistant to damagefrom processes such as wet etching, dry chemical etching, dry plasmaetching, and the like, such as silicon carbide, diamond film, silicondioxide, and the like.

In FIGS. 6A–6J, cross-sectional views of layers 600 and 602 are shown toillustrate another exemplary damascene process used to form lines andvia, such as lines 120 and plugs 119 in section 126 of FIG. 1. As willbe described below, in this exemplary process, the dielectric layer oflayer 602 includes a first sub-layer 612 and a second sub-layer 616.

With reference now to FIG. 6A, first sub-layer 612 can be formed onpreviously formed layer 600 of a semiconductor wafer, which includesinsulation layer 610, lines 606, and an optional barrier layer 608 thatcan prevent the materials in lines 606 from diffusing or leaching intodielectric layer 604. In particular, first sub-layer 612 can be formedby any convenient method, such as CVD, PVD, ALD, a spin-on coatingprocess followed by curing and drying steps, and the like. Firstsub-layer 612 can include various materials having dielectric constant(K) values less than that of silicon dioxide, such as those listed inTables 1 and 2. It should be recognized, however, that dielectric layer604 can include any materials having K values less than about 4.0.

In the present exemplary embodiment, after first sub-layer 612 is formedon previously formed layer 600, insulation layer 614 can be deposited ontop of first sub-layer 612 by any convenient deposition process, such asCVD, PVD, ALD, a spin-on coating process followed by curing and dryingsteps, and the like. As will be described below, insulation layer 614can include materials having anti-reflective properties and resistanceto lithography and etching methods, such as silicon nitride.

After insulation layer 614 is deposited on top of first sub-layer 612,second sub-layer 616 can be deposited on top of insulation layer 614 byany convenient method, such as CVD, PVD, ALD, a spin-on coating processfollowed by curing and drying steps, and the like. Second sub-layer 616can include various materials having dielectric constant (K) values lessthan that of silicon dioxide, such as those listed in Tables 1 and 2. Itshould be recognized, however, that second sub-layer 616 can include anymaterials with K values less than about 4.0.

In the present embodiment, first sub-layer 612 and second sub-layer 616are formed from materials having similar dielectric constants. However,as will be described later, first sub-layer 612 and second sub-layer 616can be formed from materials having different dielectric constants.

Referring now to FIG. 6B, trenches 618 can then be formed in secondsub-layer 616 by any convenient method, such as by lithography andetching, and the like. More particularly, the lithography method usedcan be UV lithography, deep UV lithography, x-ray lithography, electronlithography, ion beam lithography, and the like. As shown, insulationlayer 614 can separate second sub-layer 616 from first sub-layer 612,and can therefore reduce the amount of first sub-layer 612 etched awayor otherwise damaged during a lithography and etching process used toform trenches 618 in second sub-layer 616. Moreover, insulation layer614 can include anti-reflective properties that can reduce thereflection of light or UV rays from insulation layer 614 and any layersbelow that could interfere with a lithography and etching process usedto form the trenches 618 in second sub-layer 616.

In the present exemplary embodiment, after trenches 618 are formed insecond sub-layer 616, insulation layer 614 can be removed from thebottom of trenches 618 by any convenient method, such as by wet etching,dry etching, and the like.

Next, after insulation layer 614 is removed from the bottom of trenches618, via 620 can be formed in first sub-layer 612 by any convenientmethod, such as by lithography and etching, and the like. Moreparticularly, the lithography method used can be UV lithography, deep UVlithography, x-ray lithography, electron lithography, ion beamlithography, and the like. As shown, insulation layer 610 can separatefirst sub-layer 612 from dielectric material 604, lines 606, and barrierlayer 608 in previously formed layer 600, and can therefore reduce theamount of dielectric material 604, lines 606, and barrier layer 608 inpreviously formed layer 600 etched away or otherwise damaged during alithography and etching process used to form via 620 in first sub-layer612. Moreover, insulation layer 610 can include anti-reflectiveproperties that can reduce the reflection of light or UV rays frominsulation layer 610 and any layers below that could interfere with alithography and etching process used to form via 620 in first sub-layer612. It should be recognized that trench 618 and via 620 can be formedwithout using insulation layer 614.

In the present exemplary embodiment, after via 620 are formed in firstsub-layer 612, insulation layer 610 can be removed from the bottom ofvia 620 by any convenient method, such as by wet etching, dry etching,and the like. Accordingly, via 620 can connect with lines 606 inpreviously formed layer 600.

Next, with reference to FIG. 6C, adhesion layer 622 can be depositedonto layer 602 by any convenient deposition method, such as CVD, PVD,ALD, a spin-on coating process followed by curing and drying steps, andthe like. As depicted, adhesion layer 622 can line the walls of trenches618 and via 620. Additionally, adhesion layer 622 can include a materialthat can provide a smooth surface within trenches 618 and via 620,especially if dielectric layers 616 and 612 are porous or if the etchingprofile within trenches 618 and via 620 is rough. Furthermore, adhesionlayer 622 can be chosen of a material that can enhance the adhesionbetween the dielectric layers 612, 616 and a subseqently formed barrierlayer 624 (FIG. 6E), as will be described below. Examples of materialsthat can provide a smooth surface and can enhance adhesion betweendielectric layers 612, 616 and a subsequently formed barrier layer 624(FIG. 6E) include silicon dioxide, tantalum oxide, titanium oxide,tungsten oxide, silicon carbide, and the like. It should be recognized,however, that adhesion layer 622 can be omitted in some applications,such as when direct adhesion between the dielectric layers 612, 616 andbarrier layer 624 (FIG. 6E) is adequate for the particular applicationand will not adversely affect the performance of the semiconductordevice.

With reference to FIG. 6D, after adhesion layer 622 is deposited ontolayer 602, adhesion layer 622 can be removed from the bottom of via 620by any convenient method, such as anisotropic etching, and the like. Asshown, anisotropic etching can remove adhesion layer 622 from the bottomof via 620 without removing adhesion layer 622 from the walls of via620.

Next, with reference to FIG. 6E, after adhesion layer 622 is removedfrom the bottom of via 620, barrier layer 624 can be deposited ontolayer 602 by any convenient deposition method, such as CVD, PVD, ALD, aspin-on coating process followed by curing and drying steps, and thelike. As shown, barrier layer 624 can also line the walls of trenches618 and via 620. Additionally, barrier layer 624 can include a materialthat can reduce the amount of diffusion or leaching of a subsequentlyformed metal layer 628 (FIG. 6F), as will be described below, intodielectric layers 616 and 612, which can have porous microstructures.Furthermore, barrier layer 624 can be formed from a conductive material,which can adhere to dielectric layers 616 and 612, adhesion layer 622,and metal layer 628 (FIG. 6F).

As will also be described below, metal layer 624 (FIG. 6F) preferablyincludes copper. Accordingly, in the present embodiment, barrier layer624 can include material resistant to the diffusion of copper, such astitanium, tantalum, tungsten, titanium-nitride, tantalum-nitride,tungsten-nitride, tantalum silicon nitride, tungsten silicon nitride,and the like. It should be recognized, however, that barrier layer 624can be omitted in some applications. For example, when dielectric layers616 and 612 are formed from materials that are resistant to thediffusion of copper, or when the diffusion of copper into dielectriclayers 616 and 612 will not adversely affect the performance of thesemiconductor device, barrier layer 624 can be omitted.

In the present exemplary embodiment, after barrier layer 624 isdeposited onto layer 602, a seed layer 626 can be deposited on top ofbarrier layer 624 by any convenient method, such as CVD, PVD, ALD, aspin-on coating process followed by curing and drying steps, and thelike. Seed layer 626 can include the same material as subsequentlyformed metal layer 628 (FIG. 6F), as will be described below, in orderto facilitate the deposition and bonding of metal layer 628 (FIG. 6F)onto barrier layer 624, or onto adhesion layer 622 and dielectric layers616 and 612 if no barrier layer 624 is used. Accordingly, in the presentembodiment, seed layer 626 preferably includes copper. It should berecognized, however, that seed layer 626 can be omitted in someapplications. For example, when metal layer 628 (FIG. 6F) is depositedby methods such as CVD, PVD, ALD, a spin-on coating process followed bycuring and drying steps, and the like, seed layer 626 may not benecessary.

Next, with reference to FIG. 6F, metal layer 628 can be deposited ontolayer 602 by any convenient method, such as electroplating, electrolessplating, CVD, PVD, ALD, a spin-on coating process followed by curing anddrying steps, and the like. As depicted, metal layer 628 can filltrenches 618 and via 620. Additionally, metal layer 628 can includevarious electrically conductive materials, such as copper, aluminum,nickel, chromium, zinc, cadmium, silver, gold, rhodium, palladium,platinum, tin, lead, iron, indium, and the like. Furthermore, it shouldbe recognized that metal layer 628 can include an alloy of any of thevarious electrically conductive materials.

In the present exemplary embodiment, metal layer 628 preferably includescopper, and can be electroplated onto layer 602 using the electroplatingapparatus and method described in U.S. patent application, Ser. No.09/232,864, the entire content of which is incorporated herein byreference. As noted above, the deposition and bonding of metal layer 628onto barrier layer 624, or onto adhesion layer 622 and dielectric layers616 and 612 if no barrier layer 624 is used, during the electroplatingprocess can be facilitated by a previously formed seed layer 626 (FIG.6E). Additionally, as also noted above, a previously formed barrierlayer 624 can reduce the amount of diffusion or leaching of metal layer628 and an associated seed layer 626 (FIG. 6E), if used, into dielectriclayers 616 and 612. However, it should be recognized that metal layer216 can be deposited directly onto dielectric layers 616 and 612 in someapplications.

Now with reference to FIG. 6G, after metal layer 628 is deposited ontolayer 602, metal layer 628 can then be removed from the non-recessedareas of layer 602 by any convenient method, such as electropolishing,chemical-mechanical polishing (CMP), and the like. As shown, removingmetal layer 628 from the non-recessed areas of layer 602 can includeremoving metal layer 628 from non-recessed areas of any intermediatelayers, such as barrier layer 624 and the like, that are deposited ondielectric layers 616 and 612. Furthermore, as shown, in the presentembodiment, metal layer 628 is removed from non-recessed areas of layer602 while maintaining the metal layer 628 within the recessed areas(i.e., trench 618 and via 620 of FIG. 6E) of layer 602.

In the present exemplary embodiment, metal layer 628 is preferablyelectropolished from layer 602. For example, with reference to FIG. 7,metal layer 628 on semiconductor wafer 100 can be electropolished withnozzle 700. More particularly, nozzle 700 can apply an electrolytestream 704 to metal layer 628. This electrolyte stream 704 can becharged by an electrode 702. Furthermore, as depicted, a power supply706, which can operate at a constant current or constant voltage mode,can apply opposing charges to electrode 702 and metal layer 628.Accordingly, when electrolyte stream 704 is charged positively relativeto metal layer 628, metal ions can be removed from the portion of metallayer 628 in contact with electrolyte stream 704.

In the present example, electrolyte stream 704 can be applied to metallayer 628 along a spiral path by rotating semiconductor wafer 100 aboutaxis Y and translating semiconductor wafer 100 along axis X. By applyingelectrolyte stream 704 in a spiral path, metal layer 628 can beuniformly electropolished. Alternatively, electrolyte stream 704 can beapplied to metal layer 628 by holding semiconductor wafer 100 stationaryand moving nozzle 700 to apply electrolyte stream 704 to discreteportions of metal layer 628. Yet another alternative can include movingboth semiconductor wafer 100 and nozzle 700 to apply electrolyte stream704 to discrete portions of metal layer 628. For a more detaileddescription of electropolishing, see U.S. patent application Ser. No.09/497,894, entitled METHODS AND APPARATUS FOR ELECTROPOLISHING METALINTERCONNECTIONS ON SEMICONDUCTOR DEVICES, filed on Feb. 4, 2000, whichis incorporated in its entirety herein by reference.

With reference again to FIG. 6G, because electropolishing can exert lowstress on layer 602 during electropolishing, metal layer 628 can beelectropolished from layer 602 without fracturing dielectric layers 616and 612, separating metal layer 628 from dielectric layers 616 and 612,or otherwise damaging dielectric layers 616 and 612, metal layer 628, orbarrier layer 624.

Accordingly, electropolishing can provide advantages over conventionalremoval processes. In particular, polishing metal layer 628 from layer602 with CMP can cause dielectric layers 616 and 612 to fracture or pullaway from metal layer 628 due to the stress and pressure of CMP.Additionally, because electropolishing can be essentially stressless,constructing additional structures within dielectric layers 616 and 612to increase the mechanical integrity of dielectric layers 616 and 612may be unnecessary. However, it should be recognized that the presentinvention can be used with dielectric layers 616 and 612 constructedwith additional structures. Furthermore, it should also be recognizedthat a portion of metal layer 628 can be removed by CMP, or by any otherprocess, before metal layer 628 is removed from the non-recessed areasof layer 602 by electropolishing.

Referring now to FIG. 6H, after metal layer 628 is removed from thenon-recessed areas of layer 602, barrier layer 624 can be removed fromthe non-recessed areas of layer 602 by any convenient method, such aswet etching, dry chemical etching, dry plasma etching, and the like. Asnoted above, however, in some applications, barrier layer 624 may not beused.

After barrier layer 624 is removed, with reference to FIG. 61,insulation layer 630 can be deposited onto layer 602 by any convenientdeposition process, such as CVD, PVD, ALD, a spin-on coating processfollowed by curing and drying steps, and the like. As shown, insulationlayer 630 can separate layer 602 from any layers that may be depositedon top of layer 602. Additionally, insulation layer 630 can includeanti-reflective properties that can reduce the reflection of light or UVrays from insulation layer 630 and any layers below that could interferewith a lithography and etching process performed on any layers depositedabove layer 602. Moreover, insulation layer 630 can reduce the amount ofmaterials in layer 602 etched away or otherwise damaged duringlithography and etching processes that may be performed on layersdeposited above layer 602. Accordingly, in the present exemplaryembodiment, insulation layer 630 can include materials that areanti-reflective and resistant to lithography and etching methods, suchas silicon nitride.

The above process for forming layer 602 in the present embodiment can berepeated to form additional layers on top of layer 602. For instance,with reference to FIG. 6J, a first sub-layer 632, an insulation layer634, and a second sub-layer 636 can be formed on top of layer 602 toform another layer 638. Trenches and via can then be formed in layer 638to form lines and plugs, respectively, that can contact metal layer 628in layer 602.

In FIGS. 8A–8J, another exemplary embodiment of the present invention isshown. The embodiment of FIGS. 8A–8J is similar in many respects to thatof FIGS. 6A–6J, except that, with reference to FIG. 8A, the dielectriclayer of interconnection layer 602 includes a first sub-layer 800 and asecond sub-layer 802 that have different dielectric constants (K). Inthe present embodiment, as depicted in FIGS. 8A–8J, interconnectionlines (trenches 618) are formed in second sub-layer 802, and plugs (via620) are formed in first sub-layer 802.

As discussed above, as feature size is decreased, the density ofinterconnection lines increases, which can result in increasedinterconnect delays. Although the density of the plugs, which connectinterconnection lines of different layers together, also increases, itdoes not increase as rapidly as the density of the interconnectionlines.

As also discussed above, materials having lower dielectric constants Kthan silicon dioxide can be used to reduce interconnect delays. However,materials with lower K values also have lower mechanical integrity thanmaterials with higher K values.

As such, in the present embodiment, first sub-layer 800 includesmaterial having higher K values than second sub-layer 802. Thus, firstsub-layer 800 can have greater mechanical integrity and thermalconductivity than if formed from material having the same or lower Kvalue than second sub-layer 802. In this manner, the overall mechanicaland thermal conductivity of the semiconductor wafer and, consequently,the number of layers that can be formed on the semiconductor wafer canbe increased.

In the present embodiment, first sub-layer 800 can include a materialhaving an ultra-low dielectric constant, and second sub-layer 802 caninclude a material having a low dielectric constant. For example, firstsub-layer 800 can include a material with a dielectric constant ofgreater than about 2.5 and less than about 4.0, such as those materialslisted in Table 1. Second sub-layer 802 can include a material with adielectric constant of between about 1.1 and about 2.5, and preferablyabout 1.8, such as those materials list in Table 2.

In an alternative embodiment, first sub-layer 800 can include silicondioxide, and second sub-layer 802 can include a material having adielectric constant lower than silicon dioxide. For example, secondsub-layer 802 can include any of the materials listed in Tables 1 and 2that have dielectric constants lower than silicon dioxide. It should berecognized, however, that first sub-layer 800 and second sub-layer 802can include various materials depending on the particular application.

As described above, the above process for forming layer 602 in thepresent embodiment can be repeated to form additional layers on top oflayer 602. For instance, with reference to FIG. 8J, a first sub-layer804, insulation layer 634, and a second sub-layer 806 can be formed ontop of layer 603 to form another layer 638. Trenches and via can then beformed in layer 638 to form lines and plugs, respectively, that cancontact metal layer 628 in layer 602.

In FIGS. 9A–9H, another exemplary embodiment of the present invention isshown. The embodiment of FIGS. 9A–9H is similar in many respects to thatof FIGS. 8A–8J, except that, with reference to FIGS. 8C and 9C, adhesionlayer 622 is omitted. As described above, adhesion layer 622 can beomitted in some applications, such as when direct adhesion between thedielectric layer (i.e., first sub-layer 800 or second sub-layer 802) andbarrier layer 624 is adequate for the particular application and willnot adversely affect the performance of the semiconductor device.

In the following description and associated drawing figures, variousalternative embodiments will be described and depicted. It should berecognized, however, that these alternative embodiments are not intendedto demonstrate all of the various modifications that can be made to thepresent invention. Rather, these alternative embodiments are provided todemonstrate only some the many modifications that are possible withoutdeviating from the spirit and/or scope of the present invention.

In FIGS. 10A–10J, an alternative embodiment of the present invention isshown. The embodiment of FIGS. 10A–10J is similar in many respects tothat of FIGS. 6A–6J, except that, with reference to FIG. 10A, protectivelayer 1000 can be deposited on top of second sub-layer 616 by anyconvenient method, such as PVD, CVD, ALD, a spin-on coating processfollowed by curing and drying steps, and the like. Similarly, withreference to FIG. 10J, protective layer 1002 can be deposited on top ofdielectric layer 636.

With reference now to FIGS. 10G and 10OH, protective layer 1000 canseparate barrier layer 624 from second sub-layer 616, and can thereforeprotect second sub-layer 616 from damage, such as abrasion or corrosion,when barrier layer 624 is removed by any convenient method, such as wetetching, dry chemical etching, dry plasma etching, and the like.Additionally, with reference to FIGS. 10H–10J, protective layer 1000 canremain on the non-recessed areas of second sub-layer 616 during variousstages following the removal of barrier layer 624. Accordingly,protective layer 1000 can include a material that is resistant to damagefrom processes such as wet etching, dry chemical etching, dry plasmaetching, and the like, such as silicon carbide, diamond film, silicondioxide, and the like.

In FIGS. 11A–11J, another alternative embodiment of the presentinvention is shown. The embodiment of FIGS. 11A–11J is similar in manyrespects to that of FIGS. 8A–8J, except that, with reference to FIG.11A, protective layer 1000 can be deposited on top of second sub-layer802 by any convenient method, such as PVD, CVD, ALD, a spin-on coatingprocess followed by curing and drying steps, and the like. Similarly,with reference to FIG. 11J, protective layer 1002 can be deposited ontop of second sub-layer 806.

With reference now to FIGS. 11G and 11H, protective layer 1000 canseparate barrier layer 624 from second sub-layer 802, and can thereforeprotect second sub-layer 802 from damage, such as abrasion or corrosion,when barrier layer 624 is removed by any convenient method, such as wetetching, dry chemical etching, dry plasma etching, and the like.Additionally, with reference to FIGS. 11H–11J, protective layer 1000 canremain on the non-recessed areas of second sub-layer 802 during variousstages following the removal of barrier layer 624. Accordingly,protective layer 1000 can include a material that is resistant to damagefrom processes such as wet etching, dry chemical etching, dry plasmaetching, and the like, such as silicon carbide, diamond film, silicondioxide, and the like.

In FIGS. 12A–12H, yet another alternative embodiment of the presentinvention is shown. The embodiment of FIGS. 12A–12H is similar in manyrespects to that of FIGS. 9A–9H, except that with reference to FIG. 12A,protective layer 1000 can be deposited on top of second sub-layer 802 byany convenient method, such as PVD, CVD, ALD, a spin-on coating processfollowed by curing and drying steps, and the like. Similarly, withreference to FIG. 12H, protective layer 1002 can be deposited on top ofsecond sub-layer 806.

With reference now to FIGS. 12E and 12F, protective layer 1000 canseparate barrier layer 624 from second sub-layer 802, and can thereforeprotect second sub-layer 802 from damage, such as abrasion or corrosion,when barrier layer 624 is removed by any convenient method, such as wetetching, dry chemical etching, dry plasma etching, and the like.Additionally, with reference to FIGS. 12F–12H, protective layer 1000 canremain on the non-recessed areas of second sub-layer 802 during variousstages following the removal of barrier layer 624. Accordingly,protective layer 1000 can include a material that is resistant to damagefrom processes such as wet etching, dry chemical etching, dry plasmaetching, and the like, such as silicon carbide, diamond film, silicondioxide, and the like.

Although the present invention has been described with respect tocertain embodiments, examples, and applications, it will be apparent tothose skilled in the art that various modifications and changes may bemade without departing from the invention.

1. A method of forming a layer of a semiconductor wafer comprising:depositing a dielectric layer, wherein a first sub-layer of thedielectric layer is deposited and a second sub-layer of the dielectriclayer is deposited on the first sub-layer, wherein the second sub-layerhas a low dielectric constant, and wherein the dielectric constant ofthe second sub-layer is lower than the dielectric constant of the firstsub-layer; forming recessed and non-recessed areas in the dielectriclayer; depositing a metal layer on the dielectric layer to fill therecessed areas and cover the non-recessed areas; and electropolishingthe metal layer to remove the metal layer covering the non-recessedareas while maintaining the metal layer in the recessed areas.
 2. Themethod of claim 1, wherein the metal layer is electropolished discretelyfrom portions of the wafer without applying lateral stress.
 3. Themethod of claim 1, wherein forming recessed areas includes: formingtrenches for interconnection lines in the second sub-layer; and formingvia for plugs in the first sub-layer.
 4. The method of claim 1 furthercomprising: depositing an insulation layer on the first sub-layer beforedepositing the second sub-layer.
 5. The method of claim 1, wherein thefirst sub-layer includes silicon dioxide and the second sub-layerincludes a material having a dielectric constant lower than that ofsilicon dioxide.
 6. The method of claim 1, wherein the first sub-layerincludes material having a low dielectric constant and the secondsub-layer includes material having an ultra-low dielectric constant. 7.The method of claim 1, wherein the material of the first sub-layer has adielectric constant greater than about 2.5 and less than about 4.0. 8.The method of claim 7, wherein the material of the second sub-layer hasa dielectric constant of between about 1.1 and about 2.5.
 9. The methodof claim 8, wherein the material of the second sub-layer has adielectric constant of about 1.8.
 10. The method of claim 1 furthercomprising: depositing a barrier layer between the dielectric layer andthe metal layer.
 11. The method of claim 10, wherein the metal layerincludes copper.
 12. The method of claim 10 further comprising: removingthe barrier layer from the non-recessed areas after electropolishing themetal layer.
 13. The method of claim 1 further comprising: depositing anadhesion layer between the dielectric layer and the metal layer.
 14. Themethod of claim 1 further comprising: removing a portion of the metallayer using chemical-mechanical polishing prior to electropolishing themetal layer.
 15. A method of forming a layer on a semiconductor wafercomprising: depositing a dielectric layer, wherein a first sub-layer ofthe dielectric layer is deposited and a second sub-layer of thedielectric layer is deposited above the first sub-layer, and wherein thedielectric constant of the second sub-layer is lower than the dielectricconstant silicon dioxide and the first sub-layer; forming recessed andnon-recessed areas in the dielectric layer; depositing a metal layer tofill the recessed areas and cover the non-recessed areas; andelectropolishing the metal layer to remove the metal layer covering thenon-recessed areas.
 16. The method of claim 15, wherein forming recessedareas includes: forming trenches for interconnection lines in thedielectric layer; and forming via for plugs in the dielectric layer. 17.The method of claim 16, wherein the trenches for interconnection linesare formed only in the second sub-layer; and wherein the via for plugsare formed in the first sub-layer.
 18. The method of claim 17, whereinthe first sub-layer includes silicon dioxide and the second sub-layerincludes a material having a dielectric constant lower than that ofsilicon dioxide.
 19. The method of claim 18 further comprising: removingthe barrier layer from the non-recessed areas after electropolishing themetal layer.
 20. The method of claim 17, wherein the first sub-layerincludes material having a low dielectric constant and the secondsub-layer includes material having an ultra-low dielectric constant. 21.The method of claim 15 further comprising: depositing a barrier layerbetween the dielectric layer and the metal layer.
 22. The method ofclaim 21 further comprising: depositing an adhesion layer between thedielectric layer and the metal layer.
 23. The method of claim 15 furthercomprising: removing a portion of the metal layer usingchemical-mechanical polishing prior to electropolishing the metal layer.24. A method of forming a layer on a semiconductor wafer comprising:depositing a first sub-layer of a dielectric layer; depositing a secondsub-layer subsequent to the first sub-layer, the second sub-layer havinga dielectric constant less than that of silicon dioxide and the firstsub-layer; forming at least one trench in the second sub-layer; formingat least one via in the first sub-layer through the a least one trenchformed in the second sub-layer; depositing a metal layer to fill the atleast one trench formed in the second sub-layer and the at least one viaformed in the first sub-layer; and electropolishing the metal layer. 25.The method of claim 24, further comprising: after depositing the firstsub-layer and before depositing the second sub-layer, depositing a firstinsulation layer on the first sub-layer, wherein a portion of the firstinsulation layer is exposed at the bottom of the at least one trenchwhen the at least one trench is formed in the second sub-layer; andafter forming the at least one trench in the second sub-layer and beforeforming the at least one via in the first sub-layer, removing theportion of the first insulation layer exposed at the bottom of the atleast one trench.
 26. The method of claim 25, further comprising: beforedepositing the first sub-layer, depositing a second insulation layer,wherein a portion of the second insulation layer is exposed at thebottom of the at least one via when the at least one via is formed inthe first sub-layer; and after forming the at least one via in the firstsub-layer and before depositing the metal layer, removing the portion ofthe second insulation layer exposed at the bottom of the at least onevia.
 27. The method of claim 26, further comprising: after forming theat least one via and before depositing the metal layer, depositing anadhesion layer to line the walls of the at least one trench and the atleast one via; and before depositing the metal layer, removing a portionof the adhesion layer deposited on the bottom of the at least one via.28. The method of claim 27, further comprising: after removing theportion of the adhesion layer deposited on the bottom of the least onevia and before depositing the metal layer, depositing a barrier layer toadhere to the adhesion layer.